IC_CLR_TX_ABRT

         Name: Clear TX_ABRT Interrupt Register
Size: 1 bit
Address Offset: 0x54
Read/Write Access: Read

Module Instance	Base Address	Register Address
`sdm_i2c_0_DW_apb_i2c_addr_block0`	`0xFF8D0100`	`0xFF8D0154`
`sdm_i2c_1_DW_apb_i2c_addr_block1`	`0xFF8D0200`	`0xFF8D0254`

Size: 32

Offset: 0x54

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`RSVD_IC_CLR_TX_ABRT` `RO 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`RSVD_IC_CLR_TX_ABRT` `RO 0x0`															`CLR_TX_ABRT` `RO 0x0`

IC_CLR_TX_ABRT Fields

Bit	Name	Description	Access	Reset
31:1	`RSVD_IC_CLR_TX_ABRT`	Reserved bits - Read Only	`RO`	`0x0`
0	`CLR_TX_ABRT`	Read this register to clear the TX_ABRT interrupt (bit 6) of the IC_RAW_INTR_STAT register, and the IC_TX_ABRT_SOURCE register. This also releases the TX FIFO from the flushed/reset state, allowing more writes to the TX FIFO. Refer to Bit 9 of the IC_TX_ABRT_SOURCE register for an exception to clearing IC_TX_ABRT_SOURCE. Reset value: 0x0	`RO`	`0x0`

Bit

Name

Description

Access

Reset

31:1

RSVD_IC_CLR_TX_ABRT

Reserved bits - Read Only

RO

0x0

CLR_TX_ABRT

Read this register to clear the TX_ABRT
interrupt (bit 6) of the IC_RAW_INTR_STAT register,
and the IC_TX_ABRT_SOURCE register.
This also releases the TX FIFO from the flushed/reset
state, allowing more writes to the TX FIFO.
Refer to Bit 9 of the IC_TX_ABRT_SOURCE register for
an exception to clearing IC_TX_ABRT_SOURCE.
Reset value: 0x0

RO

0x0