srt

         Shadow RCVR Trigger

Module Instance	Base Address	Register Address
`i_uart_0_uart_address_block`	`0xFFC02000`	`0xFFC0209C`
`i_uart_1_uart_address_block`	`0xFFC02100`	`0xFFC0219C`

Size: 32

Offset: 0x9C

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`rsvd_srt_31to2` `RO 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`rsvd_srt_31to2` `RO 0x0`														`srt` `RW 0x0`

srt Fields

Bit

Name

Description

Access

Reset

31:2

rsvd_srt_31to2

Reserved bits [31:2] - Read Only

RO

0x0

1:0

srt

Shadow RCVR Trigger.
This is a shadow register for the RCVR trigger bits (FCR[7:6]). This can be used to
remove the burden of having to store the previously written value to the FCR in
memory and having to mask this value so that only the RCVR trigger bit gets updated.
This is used to select the trigger level in the receiver FIFO at which the Received
Data Available Interrupt will be generated. It also determines when the dma_rx_req_n
signal will be asserted when DMA Mode (FCR[3]) is set to one. The following trigger
levels are supported:
00 = 1 character in the FIFO
01 = FIFO � full
10 = FIFO � full
11 = FIFO 2 less than full

Value	Description
0	one character in fifo
1	FIFO 1/4 full
2	FIFO 1/2 full
3	FIFO 2 less than full

RW

0x0