nonmpuregion3addr_base 

         Base definition for non MPU Region 3
Module Instance Base Address Register Address
soc_noc_fw_ddr_mpu_inst_0_ddr_scr 0xF8020100 0xF80201C0

Size: 32

Offset: 0xC0

Access: RW

Access mode: SECURE | PRIVILEGEMODE

Note: The processor must make a secure, privileged bus access to this register. You can configure processor mode settings in the control registers of the ARM Cortex-A53 MPcore processor. For more information about processor modes, please refer to the ARM Infocenter.

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

high

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

low

RO 0x0

nonmpuregion3addr_base Fields

Bit Name Description Access Reset
31:16 high 
defines the 16 bit MSB of the base address field.
 RW 0x0
15:0 low 
LSB field is all zeros. Region start address is {baseext,base, 16'h000}
 RO 0x0