SSIENR

         SSI Enable Register
      
Module Instance Base Address Register Address
i_spim_0_ssi_address_block 0xFFDA4000 0xFFDA4008
i_spim_1_ssi_address_block 0xFFDA5000 0xFFDA5008

Size: 32

Offset: 0x8

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RSVD_SSIENR

RO 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RSVD_SSIENR

RO 0x0

SSI_EN

RW 0x0

SSIENR Fields

Bit Name Description Access Reset
31:1 RSVD_SSIENR
Reserved bits - Read Only
RO 0x0
0 SSI_EN
SSI Enable. Enables and disables all DW_apb_ssi operations. When
disabled, all serial transfers are halted immediately. Transmit and
receive FIFO buffers are cleared when the device is disabled. It is
impossible to program some of the DW_apb_ssi control registers when
enabled. When disabled, the ssi_sleep output is set (after delay) to
inform the system that it is safe to remove the ssi_clk, thus saving
power consumption in the system.
Value Description
0x0 Disables Serial Transfer
0x1 Enables Serial Transfer
RW 0x0