SMMU_NSCR0

         Provides top-level control of the SMMU.

Note: For register and programming information, please refer to the Arm^® CoreLink™ MMU System Memory Management Unit Technical Reference Manual.

Module Instance	Base Address	Register Address
`i_aps_smmu_secure_registers`	`0xFA000000`	`0xFA000400`

Size: 32

Offset: 0x400

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`				`WACFG` `RW 0x0`		`RACFG` `RW 0x0`		`SHCFG` `RW 0x0`		`SMCFCFG` `RO 0x1`	`MTCFG` `RW 0x0`	`MemAttr` `RW 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`BSU` `RW 0x0`		`FB` `RW 0x0`	`PTM` `RW 0x0`	`VMIDPNE` `RW 0x0`	`USFCFG` `RW 0x0`	`GSE` `RO 0x0`	`STALLD` `RO 0x0`	`TRANSIENTCFG` `RW 0x0`		`GCFGFIE` `RO 0x0`	`GCFGFRE` `RO 0x0`	`Reserved`	`GFIE` `RW 0x0`	`GFRE` `RW 0x0`	`CLIENTPD` `RW 0x1`