IC_SDA_SETUP

         Name: I2C SDA Setup Register
Size: 8 bits
Address Offset: 0x94
Read/Write Access: Read/Write
This register controls the amount of time delay
(in terms of number of ic_clk clock periods) introduced
in the rising edge of SCL, relative to SDA changing, when
DW_apb_i2c services a read request in a slave-transmitter operation.
The relevant I2C requirement is tSU:DAT (note 4) as detailed in the
I2C Bus Specification.
Dependencies: This register is not applicable  when IC_ULTRA_FAST_MODE=1

      
Module Instance Base Address Register Address
sdm_i2c_0_DW_apb_i2c_addr_block0 0xFF8D0100 0xFF8D0194
sdm_i2c_1_DW_apb_i2c_addr_block1 0xFF8D0200 0xFF8D0294

Size: 32

Offset: 0x94

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RSVD_IC_SDA_SETUP

RO 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RSVD_IC_SDA_SETUP

RO 0x0

SDA_SETUP

RW 0x64

IC_SDA_SETUP Fields

Bit Name Description Access Reset
31:8 RSVD_IC_SDA_SETUP
Reserved bits - Read Only
RO 0x0
7:0 SDA_SETUP
SDA Setup.
It is recommended that if the required delay is 1000ns,
then for an ic_clk frequency of 10 MHz, IC_SDA_SETUP
should be programmed to a value of 11.
Default Reset value: 0x64, but can be hardcoded by setting
the IC_DEFAULT_SDA_SETUP configuration parameter.
RW 0x64