srampart

Module Instance	Base Address	Register Address
`sdm_qspi_qspiregs`	`0xFF8D2000`	`0xFF8D2018`

Size: 32

Offset: 0x18

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`resv_fld` `RO 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`resv_fld` `RO 0x0`						`addr` `RW 0x80`

srampart Fields

Bit	Name	Description	Access	Reset
31:10	`resv_fld`		`RO`	`0x0`
9:0	`addr`	Defines the size of the indirect read partition in the SRAM, in units of SRAM locations. By default, half of the SRAM is reserved for indirect read operation, and half for indirect write. The size of this register will scale with the depth of the SRAM.	`RW`	`0x80`

Bit

Name

Description

Access

Reset

31:10

resv_fld

RO

0x0

9:0

addr

 Defines the size of the indirect read partition in the SRAM, in units of SRAM locations. By default, half of the SRAM is reserved for indirect read operation, and half for indirect write. The size of this register will scale with the depth of the SRAM.

RW

0x80