gmacgrp_mmc_receive_interrupt_mask
Regsiter 67 (MMC Receive Interrupt Mask Register)
The MMC Receive Interrupt Mask register maintains the masks for the interrupts generated when the receive statistic counters reach half of their maximum value, or maximum value. This register is 32-bits wide.
| Module Instance | Base Address | Register Address |
|---|---|---|
| i_emac_emac0 | 0xFF800000 | 0xFF80010C |
| i_emac_emac1 | 0xFF802000 | 0xFF80210C |
| i_emac_emac2 | 0xFF804000 | 0xFF80410C |
Size: 32
Offset: 0x10C
Access: RW
| Bit Fields | |||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|
reserved_31_26 RO 0x0 |
rxctrlfim RW 0x0 |
rxrcverrfim RW 0x0 |
rxwdogfim RW 0x0 |
rxvlangbfim RW 0x0 |
rxfovfim RW 0x0 |
rxpausfim RW 0x0 |
rxorangefim RW 0x0 |
rxlenerfim RW 0x0 |
rxucgfim RW 0x0 |
rx1024tmaxoctgbfim RW 0x0 |
|||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
rx512t1023octgbfim RW 0x0 |
rx256t511octgbfim RW 0x0 |
rx128t255octgbfim RW 0x0 |
rx65t127octgbfim RW 0x0 |
rx64octgbfim RW 0x0 |
rxosizegfim RW 0x0 |
rxusizegfim RW 0x0 |
rxjaberfim RW 0x0 |
rxruntfim RW 0x0 |
rxalgnerfim RW 0x0 |
rxcrcerfim RW 0x0 |
rxmcgfim RW 0x0 |
rxbcgfim RW 0x0 |
rxgoctim RW 0x0 |
rxgboctim RW 0x0 |
rxgbfrmim RW 0x0 |
gmacgrp_mmc_receive_interrupt_mask Fields
| Bit | Name | Description | Access | Reset | ||||||
|---|---|---|---|---|---|---|---|---|---|---|
| 31:26 | reserved_31_26 |
Reserved |
RO | 0x0 | ||||||
| 25 | rxctrlfim |
MMC Receive Control Frame Counter Interrupt Mask Setting this bit masks the interrupt when the rxctrlframes counter reaches half the maximum value, and also when it reaches the maximum value.
|
RW | 0x0 | ||||||
| 24 | rxrcverrfim |
MMC Receive Error Frame Counter Interrupt Mask Setting this bit masks the interrupt when the rxrcverror error counter reaches half the maximum value, and also when it reaches the maximum value.
|
RW | 0x0 | ||||||
| 23 | rxwdogfim |
MMC Receive Watchdog Error Frame Counter Interrupt Mask Setting this bit masks the interrupt when the rxwatchdog counter reaches half of the maximum value or the maximum value.
|
RW | 0x0 | ||||||
| 22 | rxvlangbfim |
MMC Receive VLAN Good Bad Frame Counter Interrupt Mask Setting this bit masks the interrupt when the rxvlanframes_gb counter reaches half of the maximum value or the maximum value.
|
RW | 0x0 | ||||||
| 21 | rxfovfim |
MMC Receive FIFO Overflow Frame Counter Interrupt Mask Setting this bit masks the interrupt when the rxfifooverflow counter reaches half of the maximum value or the maximum value.
|
RW | 0x0 | ||||||
| 20 | rxpausfim |
MMC Receive Pause Frame Counter Interrupt Mask Setting this bit masks the interrupt when the rxpauseframes counter reaches half of the maximum value or the maximum value.
|
RW | 0x0 | ||||||
| 19 | rxorangefim |
MMC Receive Out Of Range Error Frame Counter Interrupt Mask Setting this bit masks the interrupt when the rxoutofrangetype counter reaches half of the maximum value or the maximum value.
|
RW | 0x0 | ||||||
| 18 | rxlenerfim |
MMC Receive Length Error Frame Counter Interrupt Mask Setting this bit masks the interrupt when the rxlengtherror counter reaches half of the maximum value or the maximum value.
|
RW | 0x0 | ||||||
| 17 | rxucgfim |
MMC Receive Unicast Good Frame Counter Interrupt Mask Setting this bit masks the interrupt when the rxunicastframes_g counter reaches half of the maximum value or the maximum value.
|
RW | 0x0 | ||||||
| 16 | rx1024tmaxoctgbfim |
MMC Receive 1024 to Maximum Octet Good Bad Frame Counter Interrupt Mask Setting this bit masks the interrupt when the rx1024tomaxoctets_gb counter reaches half of the maximum value or the maximum value.
|
RW | 0x0 | ||||||
| 15 | rx512t1023octgbfim |
MMC Receive 512 to 1023 Octet Good Bad Frame Counter Interrupt Mask Setting this bit masks the interrupt when the rx512to1023octets_gb counter reaches half of the maximum value or the maximum value.
|
RW | 0x0 | ||||||
| 14 | rx256t511octgbfim |
MMC Receive 256 to 511 Octet Good Bad Frame Counter Interrupt Mask Setting this bit masks the interrupt when the rx256to511octets_gb counter reaches half of the maximum value or the maximum value.
|
RW | 0x0 | ||||||
| 13 | rx128t255octgbfim |
MMC Receive 128 to 255 Octet Good Bad Frame Counter Interrupt Mask Setting this bit masks the interrupt when the rx128to255octets_gb counter reaches half of the maximum value or the maximum value.
|
RW | 0x0 | ||||||
| 12 | rx65t127octgbfim |
MMC Receive 65 to 127 Octet Good Bad Frame Counter Interrupt Mask Setting this bit masks the interrupt when the rx65to127octets_gb counter reaches half of the maximum value or the maximum value.
|
RW | 0x0 | ||||||
| 11 | rx64octgbfim |
MMC Receive 64 Octet Good Bad Frame Counter Interrupt Mask Setting this bit masks the interrupt when the rx64octets_gb counter reaches half of the maximum value or the maximum value.
|
RW | 0x0 | ||||||
| 10 | rxosizegfim |
MMC Receive Oversize Good Frame Counter Interrupt Mask Setting this bit masks the interrupt when the rxoversize_g counter reaches half of the maximum value or the maximum value.
|
RW | 0x0 | ||||||
| 9 | rxusizegfim |
MMC Receive Undersize Good Frame Counter Interrupt Mask Setting this bit masks the interrupt when the rxundersize_g counter reaches half of the maximum value or the maximum value.
|
RW | 0x0 | ||||||
| 8 | rxjaberfim |
MMC Receive Jabber Error Frame Counter Interrupt Mask Setting this bit masks the interrupt when the rxjabbererror counter reaches half of the maximum value or the maximum value.
|
RW | 0x0 | ||||||
| 7 | rxruntfim |
MMC Receive Runt Frame Counter Interrupt Mask Setting this bit masks the interrupt when the rxrunterror counter reaches half of the maximum value or the maximum value.
|
RW | 0x0 | ||||||
| 6 | rxalgnerfim |
MMC Receive Alignment Error Frame Counter Interrupt Mask Setting this bit masks the interrupt when the rxalignmenterror counter reaches half of the maximum value or the maximum value.
|
RW | 0x0 | ||||||
| 5 | rxcrcerfim |
MMC Receive CRC Error Frame Counter Interrupt Mask Setting this bit masks the interrupt when the rxcrcerror counter reaches half of the maximum value or the maximum value.
|
RW | 0x0 | ||||||
| 4 | rxmcgfim |
MMC Receive Multicast Good Frame Counter Interrupt Mask Setting this bit masks the interrupt when the rxmulticastframes_g counter reaches half of the maximum value or the maximum value.
|
RW | 0x0 | ||||||
| 3 | rxbcgfim |
MMC Receive Broadcast Good Frame Counter Interrupt Mask Setting this bit masks the interrupt when the rxbroadcastframes_g counter reaches half of the maximum value or the maximum value.
|
RW | 0x0 | ||||||
| 2 | rxgoctim |
MMC Receive Good Octet Counter Interrupt Mask Setting this bit masks the interrupt when the rxoctetcount_g counter reaches half of the maximum value or the maximum value.
|
RW | 0x0 | ||||||
| 1 | rxgboctim |
MMC Receive Good Bad Octet Counter Interrupt Mask Setting this bit masks the interrupt when the rxoctetcount_gb counter reaches half of the maximum value or the maximum value.
|
RW | 0x0 | ||||||
| 0 | rxgbfrmim |
MMC Receive Good Bad Frame Counter Interrupt Mask Setting this bit masks the interrupt when the rxframecount_gb counter reaches half of the maximum value or the maximum value.
|
RW | 0x0 |