CPR 

         Component Parameter Register
Module Instance Base Address Register Address
i_uart_uart_address_block 0xFF8D0000 0xFF8D00F4

Size: 32

Offset: 0xF4

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RSVD_CPR_31to24

RO 0x0

FIFO_MODE

RO 0x8

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RSVD_CPR_15to14

RO 0x0

DMA_EXTRA

RO 0x1

UART_ADD_ENCODED_PARAMS

RO 0x1

SHADOW

RO 0x1

FIFO_STAT

RO 0x1

FIFO_ACCESS

RO 0x1

ADDITIONAL_FEAT

RO 0x1

SIR_LP_MODE

RO 0x0

SIR_MODE

RO 0x0

THRE_MODE

RO 0x1

AFCE_MODE

RO 0x1

RSVD_CPR_3to2

RO 0x0

APB_DATA_WIDTH

RO 0x2

CPR Fields

Bit Name Description Access Reset
31:24 RSVD_CPR_31to24 
Reserved bits [31:24] - Read Only
 RO 0x0
23:16 FIFO_MODE 
Encoding of FIFO_MODE configuration parameter value.DW_apb_uart.ralf
0x00 = 0,
0x01 = 16,
0x02 = 32,
toset
0x80 = 2048,
0x81- 0xff = reserved
Value Description
0x0 FIFO mode is 0
0x1 FIFO mode is 16
0x2 FIFO mode is 32
0x4 FIFO mode is 64
0x8 FIFO mode is 128
0x10 FIFO mode is 256
0x20 FIFO mode is 512
0x40 FIFO mode is 1024
0x80 FIFO mode is 2048
RO 0x8
15:14 RSVD_CPR_15to14 
Reserved bits [15:14] - Read Only
 RO 0x0
13 DMA_EXTRA 
Encoding of DMA_EXTRA configuration parameter value.
0 = FALSE,DW_apb_uart.ralf
1 = TRUE
Value Description
0x0 DMA_EXTRA disabled
0x1 DMA_EXTRA enabled
RO 0x1
12 UART_ADD_ENCODED_PARAMS 
Encoding of UART_ADD_ENCODED_PARAMS configuration parameter value.
0 = FALSE,
1 = TRUE
Value Description
0x0 UART_ADD_ENCODED_PARAMS disabled
0x1 UART_ADD_ENCODED_PARAMS enabled
RO 0x1
11 SHADOW 
Encoding of SHADOW configuration parameter value.
0 = FALSE,
1 = TRUE
Value Description
0x0 SHADOW disabled
0x1 SHADOW enabled
RO 0x1
10 FIFO_STAT 
Encoding of FIFO_STAT configuration parameter value.
0 = FALSE,
1 = TRUE
Value Description
0x0 FIFO_STAT disabled
0x1 FIFO_STAT enabled
RO 0x1
9 FIFO_ACCESS 
Encoding of FIFO_ACCESS configuration parameter value.
0 = FALSE,
1 = TRUE
Value Description
0x0 FIFO_ACCESS disabled
0x1 FIFO ACCESS enabled
RO 0x1
8 ADDITIONAL_FEAT 
Encoding of ADDITIONAL_FEATURES configuration parameter value.
0 = FALSE,
1 = TRUE
Value Description
0x0 Additional features disabled
0x1 Additional features enabled
RO 0x1
7 SIR_LP_MODE 
Encoding of SIR_LP_MODE configuration parameter value.
0 = FALSE,
1 = TRUE
Value Description
0x0 SIR_LP mode disabled
0x1 SIR_LP mode enabled
RO 0x0
6 SIR_MODE 
Encoding of SIR_MODE configuration parameter value.
0 = FALSE,
1 = TRUE
Value Description
0x0 SIR mode disabled
0x1 SIR mode enabled
RO 0x0
5 THRE_MODE 
Encoding of THRE_MODE configuration parameter value.
0 = FALSE,
1 = TRUE
Value Description
0x0 THRE mode disabled
0x1 THRE mode enabled
RO 0x1
4 AFCE_MODE 
Encoding of AFCE_MODE configuration parameter value.
0 = FALSE,
1 = TRUE
Value Description
0x0 AFCE mode disabled
0x1 AFCE mode enabled
RO 0x1
3:2 RSVD_CPR_3to2 
Reserved bits [3:2] - Read Only
 RO 0x0
1:0 APB_DATA_WIDTH 
Encoding of APB_DATA_WIDTH configuration parameter value.
00 = 8 bits,
01 = 16 bits,
10 = 32 bits,
11 = reserved
Value Description
0x0 APB data width is 8 bits
0x1 APB data width is 16 bits
0x2 APB data width is 32 bits
RO 0x2