gmacgrp_pps0_width

         
The PPS0 Width register contains the number of units of sub-second increment value between the rising and corresponding falling edges of the PPS0 signal output (ptp_pps_o[0]).
      
Module Instance Base Address Register Address
i_emac_emac0 0xFF800000 0xFF800764
i_emac_emac1 0xFF802000 0xFF802764
i_emac_emac2 0xFF804000 0xFF804764

Size: 32

Offset: 0x764

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

ppswidth

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ppswidth

RW 0x0

gmacgrp_pps0_width Fields

Bit Name Description Access Reset
31:0 ppswidth
These bits store the width between the rising edge and corresponding falling edge of the PPS0 signal output in terms of units of sub-second increment value. 

You need to program one value less than the required interval. For example, if PTP reference clock is 50 MHz (period of 20ns), and desired width between the rising and corresponding falling edges of PPS0 signal output is 80ns (that is, four units of sub-second increment value), then you should program value 3 (4-1) in this register.

Note: 
The value programmed in this register must be lesser than the value programmed in Register 472 (PPS0 Interval Register).
RW 0x0