GPIO_CONFIG_REG1 

         Name: GPIO Configuration Register 1
Size: 32 bits
Address Offset: 0x74
Read/Write Access: Read
Module Instance Base Address Register Address
i_gpio_0_DW_apb_gpio_addr_block 0xFFC03200 0xFFC03274
i_gpio_1_DW_apb_gpio_addr_block 0xFFC03300 0xFFC03374

Size: 32

Offset: 0x74

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

INTERRUPT_BOTH_EDGE_TYPE

RO 0x0

ENCODED_ID_WIDTH

RO 0x1F

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

GPIO_ID

RO 0x1

ADD_ENCODED_PARAMS

RO 0x1

DEBOUNCE

RO 0x1

PORTA_INTR

RO 0x1

HW_PORTD

RO 0x0

HW_PORTC

RO 0x0

HW_PORTB

RO 0x0

HW_PORTA

RO 0x0

PORTD_SINGLE_CTL

RO 0x1

PORTC_SINGLE_CTL

RO 0x1

PORTB_SINGLE_CTL

RO 0x1

PORTA_SINGLE_CTL

RO 0x1

NUM_PORTS

RO 0x0

APB_DATA_WIDTH

RO 0x2

GPIO_CONFIG_REG1 Fields

Bit Name Description Access Reset
21 INTERRUPT_BOTH_EDGE_TYPE 
The value of this register is derived from the 
GPIO_INT_BOTH_EDGE configuration parameter
Value Description
0x0 Interrupt generation on rising or falling edge
0x1 Interrupt generation on both rising and falling edge
RO 0x0
20:16 ENCODED_ID_WIDTH 
The value of this register is derived from the
GPIO_ID_WIDTH configuration parameter.
 RO 0x1F
15 GPIO_ID 
The value of this register is derived from the
GPIO_ID configuration parameter.
0 = Exclude
1 = Include
Value Description
0x0 GPIO_ID not included
0x1 GPIO_ID is included
RO 0x1
14 ADD_ENCODED_PARAMS 
The value of this register is derived from the
GPIO_ADD_ENCODED_PARAMS configuration parameter.
0 = False
1 = True
Value Description
0x0 Encoded parameters not added
0x1 Encoded parameters added
RO 0x1
13 DEBOUNCE 
The value of this register is derived from the
GPIO_DEBOUNCE configuration parameter.
0 = Exclude
1 = Include
Value Description
0x0 Exclude debounce capability
0x1 Include debounce capability
RO 0x1
12 PORTA_INTR 
The value of this register is derived from the
GPIO_PORTA_INTR configuration parameter.
0 = Exclude
1 = Include
Value Description
0x0 PORT A is not used as an interrupt source
0x1 PORT A is required to be used as an interrupt source
RO 0x1
11 HW_PORTD 
The value of this register is derived from the
GPIO_HW_PORTD configuration parameter.
0 = Exclude
1 = Include
Value Description
0x0 Port D has external, auxiliary hardware signals excluded
0x1 Port D has external, auxiliary hardware signals included
RO 0x0
10 HW_PORTC 
The value of this register is derived from the
GPIO_HW_PORTC configuration parameter.
0 = Exclude
1 = Include
Value Description
0x0 Port C has external, auxiliary hardware signals excluded
0x1 Port C has external, auxiliary hardware signals included
RO 0x0
9 HW_PORTB 
The value of this register is derived from the
GPIO_HW_PORTB configuration parameter.
0 = Exclude
1 = Include
Value Description
0x0 Port B has external, auxiliary hardware signals excluded
0x1 Port B has external, auxiliary hardware signals included
RO 0x0
8 HW_PORTA 
The value of this register is derived from the
GPIO_HW_PORTA configuration parameter.
0 = Exclude
1 = Include
Value Description
0x0 Port A has external, auxiliary hardware signals excluded
0x1 Port A has external, auxiliary hardware signals included
RO 0x0
7 PORTD_SINGLE_CTL 
The value of this register is derived from the
GPIO_PORTD_SINGLE_CTL configuration parameter.
0 = False
1 = True
Value Description
0x0 PORTD is not controlled from a single source
0x1 PORTD is controlled from a single source
RO 0x1
6 PORTC_SINGLE_CTL 
The value of this register is derived from the
GPIO_PORTC_SINGLE_CTL configuration parameter.
0 = False
1 = True
Value Description
0x0 PORTC is not controlled from a single source
0x1 PORTC is controlled from a single source
RO 0x1
5 PORTB_SINGLE_CTL 
The value of this register is derived from the
GPIO_PORTB_SINGLE_CTL configuration parameter.
0 = False
1 = True
Value Description
0x0 PORTB is not controlled from a single source
0x1 PORTB is controlled from a single source
RO 0x1
4 PORTA_SINGLE_CTL 
The value of this register is derived from the
GPIO_PORTA_SINGLE_CTL configuration parameter.
0 = False
1 = True
Value Description
0x0 PORTA is not controlled from a single source
0x1 PORTA is controlled from a single source
RO 0x1
3:2 NUM_PORTS 
The value of this register is derived from the
GPIO_NUM_PORT configuration parameter.
0x0 = 1
0x1 = 2
0x2 = 3
0x3 = 4
Value Description
0x0 Number of ports is 1
0x1 Number of ports is 2
0x2 Number of ports is 3
0x3 Number of ports is 4
RO 0x0
1:0 APB_DATA_WIDTH 
The value of this register is derived from the
GPIO_APB_DATA_WIDTH configuration parameter.
0x0 = 8 bits
0x1 = 16 bits
0x2 = 32 bits
0x3 = Reserved
Value Description
0x0 APB DATA WIDTH is 8 bits
0x1 APB DATA WIDTH is 16 bits
0x2 APB DATA WIDTH is 32 bits
RO 0x2