ddr_T_main_Probe_StatAlarmClr

         DDR Main Probe Statistics Alarm Clear Register

Module Instance	Base Address	Register Address
`soc_ddr_scheduler_inst_0_ddr_T_main_Probe`	`0xF8000000`	`0xF8000038`

Size: 32

Offset: 0x38

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved`															`STATALARMCLR` `RW 0x0`

ddr_T_main_Probe_StatAlarmClr Fields

Bit	Name	Description	Access	Reset
0	`STATALARMCLR`	Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False, StatAlarmClr is reserved.NOTE The written value is not stored in StatAlarmClr. A read always returns 0.	`RW`	`0x0`

Bit

Name

Description

Access

Reset

STATALARMCLR

Register StatAlarmClr is a 1-bit register. Writing a 1 to this register clears the StatAlarmStatus register bit.When parameter statisticsCounterAlarm is set to False, StatAlarmClr is reserved.NOTE  The written value is not stored in StatAlarmClr. A read always returns 0.

RW

0x0