fpga2sdram0_axi32_I_main_QosGenerator_Bandwidth
FPGA2SDRAM0 AXI-32 QoS Generator Bandwidth Register
| Module Instance | Base Address | Register Address |
|---|---|---|
| soc_ddr_scheduler_inst_0_fpga2sdram0_axi32_I_main_QosGenerator | 0xF8022180 | 0xF8022190 |
Size: 32
Offset: 0x10
Access: RW
Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
| Bit Fields | |||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|
Reserved |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
Reserved |
BANDWIDTH RW 0x280 |
||||||||||||||
fpga2sdram0_axi32_I_main_QosGenerator_Bandwidth Fields
| Bit | Name | Description | Access | Reset |
|---|---|---|---|---|
| 10:0 | BANDWIDTH |
In Bandwidth Limiter or Bandwidth Regulator mode, the bandwidth threshold in units of 1/256th bytes per cycle. For example, 80 MBps on a 250 MHz interface is value 0x0052. |
RW | 0x280 |