enable_clear 

         Clears Master Region Enable field when written with 1
Module Instance Base Address Register Address
soc_noc_fw_ddr_fpga2sdram_inst_0_ddr_scr 0xF8020200 0xF8020208

Size: 32

Offset: 0x8

Access: WO

Access mode: SECURE | PRIVILEGEMODE

Note: The processor must make a secure, privileged bus access to this register. You can configure processor mode settings in the control registers of the ARM Cortex-A53 MPcore processor. For more information about processor modes, please refer to the ARM Infocenter.

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

region3enable

WO 0x0

region2enable

WO 0x0

region1enable

WO 0x0

region0enable

WO 0x0

enable_clear Fields

Bit Name Description Access Reset
3 region3enable 
Region 3 Enable Clear.
Writing zero has no effect
Writing one will clear the region3enable bit to zero
 WO 0x0
2 region2enable 
Region 2 Enable Clear.
Writing zero has no effect
Writing one will clear the region2enable bit to zero
 WO 0x0
1 region1enable 
Region 1 Enable Clear.
Writing zero has no effect
Writing one will clear the region1enable bit to zero
 WO 0x0
0 region0enable 
Region 0 Enable Clear.
Writing zero has no effect
Writing one will clear the region0enable bit to zero
 WO 0x0