gmacgrp_mmc_ipc_receive_interrupt
This register maintains the interrupts generated when receive IPC statistic counters reach half their maximum values (0x8000_0000 for 32-bit counter and 0x8000 for 16-bit counter), and when they cross their maximum values (0xFFFF_FFFF for 32-bit counter and 0xFFFF for 16-bit counter). When Counter Stop Rollover is set, then interrupts are set but the counter remains at all-ones. The MMC Receive Checksum Offload Interrupt register is 32-bits wide. When the MMC IPC counter that caused the interrupt is read, its corresponding interrupt bit is cleared. The counter's least-significant byte lane (bits[7:0]) must be read to clear the interrupt bit.
| Module Instance | Base Address | Register Address |
|---|---|---|
| i_emac_emac0 | 0xFF800000 | 0xFF800208 |
| i_emac_emac1 | 0xFF802000 | 0xFF802208 |
| i_emac_emac2 | 0xFF804000 | 0xFF804208 |
Size: 32
Offset: 0x208
Access: RO
| Bit Fields | |||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|
Reserved |
rxicmperois RO 0x0 |
rxicmpgois RO 0x0 |
rxtcperois RO 0x0 |
rxtcpgois RO 0x0 |
rxudperois RO 0x0 |
rxudpgois RO 0x0 |
rxipv6nopayois RO 0x0 |
rxipv6herois RO 0x0 |
rxipv6gois RO 0x0 |
rxipv4udsblois RO 0x0 |
rxipv4fragois RO 0x0 |
rxipv4nopayois RO 0x0 |
rxipv4herois RO 0x0 |
rxipv4gois RO 0x0 |
|
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
Reserved |
rxicmperfis RO 0x0 |
rxicmpgfis RO 0x0 |
rxtcperfis RO 0x0 |
rxtcpgfis RO 0x0 |
rxudperfis RO 0x0 |
rxudpgfis RO 0x0 |
rxipv6nopayfis RO 0x0 |
rxipv6herfis RO 0x0 |
rxipv6gfis RO 0x0 |
rxipv4udsblfis RO 0x0 |
rxipv4fragfis RO 0x0 |
rxipv4nopayfis RO 0x0 |
rxipv4herfis RO 0x0 |
rxipv4gfis RO 0x0 |
|
gmacgrp_mmc_ipc_receive_interrupt Fields
| Bit | Name | Description | Access | Reset | ||||||
|---|---|---|---|---|---|---|---|---|---|---|
| 29 | rxicmperois |
This bit is set when the rxicmp_err_octets counter reaches half of the maximum value or the maximum value.
|
RO | 0x0 | ||||||
| 28 | rxicmpgois |
This bit is set when the rxicmp_gd_octets counter reaches half of the maximum value or the maximum value.
|
RO | 0x0 | ||||||
| 27 | rxtcperois |
This bit is set when the rxtcp_err_octets counter reaches half of the maximum value or the maximum value.
|
RO | 0x0 | ||||||
| 26 | rxtcpgois |
This bit is set when the rxtcp_gd_octets counter reaches half the maximum value or the maximum value.
|
RO | 0x0 | ||||||
| 25 | rxudperois |
This bit is set when the rxudp_err_octets counter reaches half the maximum value or the maximum value.
|
RO | 0x0 | ||||||
| 24 | rxudpgois |
This bit is set when the rxudp_gd_octets counter reaches half of the maximum value or the maximum value.
|
RO | 0x0 | ||||||
| 23 | rxipv6nopayois |
This bit is set when the rxipv6_nopay_octets counter reaches half of the maximum value or the maximum value.
|
RO | 0x0 | ||||||
| 22 | rxipv6herois |
This bit is set when the rxipv6_hdrerr_octets counter reaches half of the maximum value or the maximum value.
|
RO | 0x0 | ||||||
| 21 | rxipv6gois |
This bit is set when the rxipv6_gd_octets counter reaches half of the maximum value or the maximum value.
|
RO | 0x0 | ||||||
| 20 | rxipv4udsblois |
This bit is set when the rxipv4_udsbl_octets counter reaches half of the maximum value or the maximum value.
|
RO | 0x0 | ||||||
| 19 | rxipv4fragois |
This bit is set when the rxipv4_frag_octets counter reaches half of the maximum value or the maximum value.
|
RO | 0x0 | ||||||
| 18 | rxipv4nopayois |
This bit is set when the rxipv4_nopay_octets counter reaches half of the maximum value or the maximum value.
|
RO | 0x0 | ||||||
| 17 | rxipv4herois |
This bit is set when the rxipv4_hdrerr_octets counter reaches half of the maximum value or the maximum value.
|
RO | 0x0 | ||||||
| 16 | rxipv4gois |
This bit is set when the rxipv4_gd_octets counter reaches half of the maximum value or the maximum value.
|
RO | 0x0 | ||||||
| 13 | rxicmperfis |
This bit is set when the rxicmp_err_frms counter reaches half of the maximum value or the maximum value.
|
RO | 0x0 | ||||||
| 12 | rxicmpgfis |
This bit is set when the rxicmp_gd_frms counter reaches half of the maximum value or the maximum value.
|
RO | 0x0 | ||||||
| 11 | rxtcperfis |
This bit is set when the rxtcp_err_frms counter reaches half of the maximum value or the maximum value.
|
RO | 0x0 | ||||||
| 10 | rxtcpgfis |
This bit is set when the rxtcp_gd_frms counter reaches half of the maximum value or the maximum value.
|
RO | 0x0 | ||||||
| 9 | rxudperfis |
This bit is set when the rxudp_err_frms counter reaches half of the maximum value or the maximum value.
|
RO | 0x0 | ||||||
| 8 | rxudpgfis |
This bit is set when the rxudp_gd_frms counter reaches half of the maximum value or the maximum value.
|
RO | 0x0 | ||||||
| 7 | rxipv6nopayfis |
This bit is set when the rxipv6_nopay_frms counter reaches half of the maximum value or the maximum value.
|
RO | 0x0 | ||||||
| 6 | rxipv6herfis |
This bit is set when the rxipv6_hdrerr_frms counter reaches half of the maximum value or the maximum value.
|
RO | 0x0 | ||||||
| 5 | rxipv6gfis |
This bit is set when the rxipv6_gd_frms counter reaches half of the maximum value or the maximum value.
|
RO | 0x0 | ||||||
| 4 | rxipv4udsblfis |
This bit is set when the rxipv4_udsbl_frms counter reaches half of the maximum value or the maximum value.
|
RO | 0x0 | ||||||
| 3 | rxipv4fragfis |
This bit is set when the rxipv4_frag_frms counter reaches half of the maximum value or the maximum value.
|
RO | 0x0 | ||||||
| 2 | rxipv4nopayfis |
This bit is set when the rxipv4_nopay_frms counter reaches half of the maximum value or the maximum value.
|
RO | 0x0 | ||||||
| 1 | rxipv4herfis |
This bit is set when the rxipv4_hdrerr_frms counter reaches half of the maximum value or the maximum value.
|
RO | 0x0 | ||||||
| 0 | rxipv4gfis |
This bit is set when the rxipv4_gd_frms counter reaches half of the maximum value or the maximum value.
|
RO | 0x0 |