ECC_accctrl

         These bits determine which byte of data/ecc to write to RAM.
      
Module Instance Base Address Register Address
sdm_ecc_nand_w_ecc_registerBlock 0xFFA20800 0xFFA20878

Size: 32

Offset: 0x78

Access: RW

Access mode: PRIVILEGEMODE

Note: The processor must make a privileged bus access to this register. You can configure processor mode settings in the control registers of the ARM Cortex-A53 MPcore processor. For more information about processor modes, please refer to the ARM Infocenter.

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

RDWR

0x0

Reserved

ECCOVR

0x0

DATAOVR

0x0

ECC_accctrl Fields

Bit Name Description Access Reset
8 RDWR
Control for read/write.
RW 0x0
1 ECCOVR
ECC Data Override.
RW 0x0
0 DATAOVR
RAM Data Override. Override the ECC_dataBUS register with RAM data in read mode set by ECC_RW. 
1’b0: Data override disabled. 
1’b1: Data override enabled.
RW 0x0