smmu_cb26_pmauthstatus

         Provides the equivalent of the PMAUTHSTATUS register, in the register map of a translation context bank. Indicates the implemented debug features and provides the current values of the configuration inputs that determine the debug permissions

Note: For register and programming information, please refer to the Arm^® CoreLink™ MMU System Memory Management Unit Technical Reference Manual.

Module Instance	Base Address	Register Address
`i_aps_smmu_secure_registers`	`0xFA000000`	`0xFA03AFB8`

Size: 32

Offset: 0x3AFB8

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved`								`SNI` `RO 0x1`	`SNE` `RO 0x0`	`SI` `RO 0x0`	`SE` `RO 0x0`	`NSNI` `RO 0x0`	`NSNE` `RO 0x0`	`NSI` `RO 0x0`	`NSE` `RO 0x0`