reg_caltiming4

         Calibration Timing 4 Register

Module Instance	Base Address	Register Address
`iohmc_ctrl_inst_0_iohmc_ctrl_mmr_top_inst`	`0xF8010000`	`0xF801008C`

Size: 32

Offset: 0x8C

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`cfg_t_param_pdn_to_valid` `RO 0x0`						`cfg_t_param_arf_to_valid` `RO 0x0`								`cfg_t_param_pch_all_to_valid` `RO 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`cfg_t_param_pch_all_to_valid` `RO 0x0`				`cfg_t_param_pch_to_valid` `RO 0x0`						`cfg_t_param_wr_ap_to_valid` `RO 0x0`

reg_caltiming4 Fields

Bit	Name	Description	Access	Reset
31:26	`cfg_t_param_pdn_to_valid`	iohmc_ctrl_mmr_top_inst.cfg_t_param_pdn_to_valid[5:0] Name:Power Down to Valid Description:Power down to valid bank command window.	`RO`	`0x0`
25:18	`cfg_t_param_arf_to_valid`	iohmc_ctrl_mmr_top_inst.cfg_t_param_arf_to_valid[7:0] Name:Auto Refresh to Valid Description:Auto Refresh to valid DRAM command window. When operating in DDR4 3DS mode, this register serves as the SLR (same logical rank) variant of tRFC.	`RO`	`0x0`
17:12	`cfg_t_param_pch_all_to_valid`	iohmc_ctrl_mmr_top_inst.cfg_t_param_pch_all_to_valid[5:0] Name:Precharge All to Valid Description:Precharge all to banks being ready for bank activation command.	`RO`	`0x0`
11:6	`cfg_t_param_pch_to_valid`	iohmc_ctrl_mmr_top_inst.cfg_t_param_pch_to_valid[5:0] Name:Precharge to Valid Description:Precharge to valid command timing.	`RO`	`0x0`
5:0	`cfg_t_param_wr_ap_to_valid`	iohmc_ctrl_mmr_top_inst.cfg_t_param_wr_ap_to_valid[5:0] Name:Wr with Auto Precharge to Valid Description:Write with autoprecharge to valid command timing.	`RO`	`0x0`