tcwaw_and_addr_2_data

         
      
Module Instance Base Address Register Address
i_nand_config 0xFFB80000 0xFFB80110

Size: 32

Offset: 0x110

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

tcwaw

RW 0x14

Reserved

addr_2_data

RW 0x32

tcwaw_and_addr_2_data Fields

Bit Name Description Access Reset
13:8 tcwaw
Signifies the number of controller clocks that should be introduced between 
                  the command cycle of a random data input command to the address cycle of the random
                  data input command. 
RW 0x14
6:0 addr_2_data
Signifies the number of bus interface clk_x clocks that should be introduced 
                  between an address to a data input cycle. The number of clocks is the function of device 
                  parameter Tadl and controller clock frequency.
RW 0x32