IC_ENABLE

         Name: I2C Enable Register
Size: 18 bits
Address Offset: 0x6c
Read/Write Access: Read/Write
Bit 16 is read only when IC_SMBUS=0.
Bits 17 & 18 are read only when IC_SMBUS_SUSPEND_ALERT=0.

Module Instance	Base Address	Register Address
`sdm_i2c_0_DW_apb_i2c_addr_block0`	`0xFF8D0100`	`0xFF8D016C`
`sdm_i2c_1_DW_apb_i2c_addr_block1`	`0xFF8D0200`	`0xFF8D026C`

Size: 32

Offset: 0x6C

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`RSVD_IC_ENABLE_2` `RO 0x0`													`RSVD_SMBUS_ALERT_EN` `RO 0x0`	`RSVD_SMBUS_SUSPEND_EN` `RO 0x0`	`RSVD_SMBUS_CLK_RESET` `RO 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`RSVD_IC_ENABLE_1` `RO 0x0`												`RSVD_SDA_STUCK_RECOVERY_ENABLE` `RO 0x0`	`TX_CMD_BLOCK` `RW 0x0`	`ABORT` `RW 0x0`	`ENABLE` `RW 0x0`

IC_ENABLE Fields

Bit

Name

Description

Access

Reset

31:19

RSVD_IC_ENABLE_2

Reserved bits - Read Only

RO

0x0

RSVD_SMBUS_ALERT_EN

Reserved bits - Read Only

RO

0x0

RSVD_SMBUS_SUSPEND_EN

Reserved bits - Read Only

RO

0x0

RSVD_SMBUS_CLK_RESET

Reserved bits - Read Only

RO

0x0

15:4

RSVD_IC_ENABLE_1

Reserved bits - Read Only

RO

0x0

RSVD_SDA_STUCK_RECOVERY_ENABLE

Reserved bits - Read Only

RO

0x0

TX_CMD_BLOCK

In Master mode
1'b1  blocks the transmission of data on I2C bus even if Tx FIFO has data to transmit.
1'b0  The transmission of data starts on I2C bus automatically, as soon as the first data is available in the Tx FIFO.
Reset value : IC_TX_CMD_BLOCK_DEFAULT 
Dependencies: This Register bit value is  applicable only when IC_TX_CMD_BLOCK =1

NOTE:In order to block the execution of Master commands,
set the TX_CMD_BLOCK bit only when  Tx FIFO is empty (IC_STATUS[2]==1) and Master is in Idle state (IC_STATUS[5] == 0). 
Then any further commands put in the Tx FIFO will not get executed until TX_CMD_BLOCK bit is unset.

Value	Description
0x0	Tx Command execution not blocked
0x1	Tx Command execution blocked

RW

0x0

ABORT

When set, the controller initiates the transfer abort.
0: ABORT not initiated or ABORT done
1: ABORT operation in progress
The software can abort the I2C transfer in master mode by setting this bit. The software 
can set this bit only when ENABLE is already set; otherwise, the controller ignores any 
write to ABORT bit. The software cannot clear the ABORT bit once set. In response to 
an ABORT, the controller issues a STOP and flushes the Tx FIFO after completing the 
current transfer, then sets the TX_ABORT interrupt after the abort operation. The 
ABORT bit is cleared automatically after the abort operation.
Reset value: 0x0

Value	Description
0x0	ABORT operation not in progress
0x1	ABORT operation in progress

RW

0x0

ENABLE

Controls whether the DW_apb_i2c is enabled.
0: Disables DW_apb_i2c (TX and RX FIFOs are
   held in an erased state)
1: Enables DW_apb_i2c
Software can disable DW_apb_i2c while it is active.
However, it is important that care be taken to ensure
that DW_apb_i2c is disabled properly.
When DW_apb_i2c is disabled, the following occurs:
- The TX FIFO and RX FIFO get flushed.
- Status bits in the IC_INTR_STAT register are still
  active until DW_apb_i2c goes into IDLE state.
If the module is transmitting, it stops as well as deletes
the contents of the transmit buffer after the current transfer
is complete. If the module is receiving, the DW_apb_i2c stops
the current transfer at the end of the current byte and does not
acknowledge the transfer.
In systems with asynchronous pclk and ic_clk when IC_CLK_TYPE
parameter set to asynchronous (1), there is a two ic_clk delay
when enabling or disabling the DW_apb_i2c.
Reset value: 0x0

Value	Description
0x0	I2C is disabled
0x1	I2C is enabled

RW

0x0