SERRCNTREG

         Maximum counter value for single-bit error interrupt

Module Instance	Base Address	Register Address
`soc_hmc_adp_csr_inst_0_ocp_slv_block`	`0xF8011000`	`0xF801113C`

Size: 32

Offset: 0x13C

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`SERRCNT` `0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`SERRCNT` `0x0`

SERRCNTREG Fields

Bit	Name	Description	Access	Reset
31:0	`SERRCNT`	Compare value for the internal single-bit errors. This register sets the value to compare with the internal counter. Software should write to this register before enabling the interrupt on compare. 0x0: If the serrcnt bits are not modified before enabling the intoncmp, internal counter=0 and serrcnt=0, serr compare interrupt will not occur. Default after reset. Nonzero: if internal counter == serrcnt == nonzero will create a serr compare interrupt. When the compare matches, autoWB_drop_cmpflga will be set.	`RW`	`0x0`

Bit

Name

Description

Access

Reset

31:0

SERRCNT

Compare value for the internal single-bit errors.
This register sets the value to compare with the internal counter. Software should write to this register before enabling the interrupt on compare.   
0x0: If the serrcnt bits are not modified before enabling the intoncmp, internal counter=0 and serrcnt=0, serr compare interrupt will not occur. Default after reset.
Nonzero: if internal counter == serrcnt == nonzero will create a serr compare interrupt. 
When the compare matches, autoWB_drop_cmpflga will be set.

RW

0x0