dmagrp_transmit_descriptor_list_address 

         Register 4 (Transmit Descriptor List Address Register)

The Transmit Descriptor List Address register points to the start of the Transmit Descriptor List. The descriptor lists reside in the host's physical memory space and must be Word, Dword, or Lword-aligned (for 32-bit, 64-bit, or 128-bit data bus). The DMA internally converts it to bus width aligned address by making the corresponding LSB to low. 

You can write to this register only when the Tx DMA has stopped, that is, Bit 13 (ST) is set to zero in Register 6 (Operation Mode Register). When stopped, this register can be written with a new descriptor list address. When you set the ST bit to 1, the DMA takes the newly programmed descriptor base address.

If this register is not changed when the ST bit is set to 0, then the DMA takes the descriptor address where it was stopped earlier.
Module Instance Base Address Register Address
i_emac_emac0 0xFF800000 0xFF801010
i_emac_emac1 0xFF802000 0xFF803010
i_emac_emac2 0xFF804000 0xFF805010

Size: 32

Offset: 0x1010

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

tdesla_32bit

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

tdesla_32bit

RW 0x0

Reserved

dmagrp_transmit_descriptor_list_address Fields

Bit Name Description Access Reset
31:2 tdesla_32bit 
This field contains the base address of the first descriptor in the Transmit Descriptor list. The LSB bits (1:0) are ignored (32-bit wide bus) and are internally taken as all-zero by the DMA. Therefore, these LSB bits are read-only (RO).
 RW 0x0