ICR

         Interrupt Clear Register

Module Instance	Base Address	Register Address
`i_spim_0_ssi_address_block`	`0xFFDA4000`	`0xFFDA4048`
`i_spim_1_ssi_address_block`	`0xFFDA5000`	`0xFFDA5048`

Size: 32

Offset: 0x48

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`RSVD_ICR` `RO 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`RSVD_ICR` `RO 0x0`															`ICR` `RO 0x0`

ICR Fields

Bit	Name	Description	Access	Reset
31:1	`RSVD_ICR`	Reserved bits - Read Only	`RO`	`0x0`
0	`ICR`	Clear Interrupts. This register is set if any of the interrupts below are active. A read clears the ssi_txo_intr, ssi_rxu_intr, ssi_rxo_intr, and the ssi_mst_intr interrupts. Writing to this register has no effect.	`RO`	`0x0`

Bit

Name

Description

Access

Reset

31:1

RSVD_ICR

Reserved bits - Read Only

RO

0x0

ICR

Clear Interrupts.
This register is set if any of the interrupts below are active. A read
clears the ssi_txo_intr, ssi_rxu_intr, ssi_rxo_intr, and the ssi_mst_intr
interrupts. Writing to this register has no effect.

RO

0x0