fpga2sdram0_axi128_I_main_QosGenerator_Saturation

         FPGA2SDRAM0 AXI-128 QoS Generator Saturation Value Register

Module Instance	Base Address	Register Address
`soc_ddr_scheduler_inst_0_fpga2sdram0_axi128_I_main_QosGenerator`	`0xF8022100`	`0xF8022114`

Size: 32

Offset: 0x14

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved`						`SATURATION` `RW 0x8`

fpga2sdram0_axi128_I_main_QosGenerator_Saturation Fields

Bit	Name	Description	Access	Reset
9:0	`SATURATION`	In Bandwidth Limiter or Bandwidth Regulator mode, the maximum data count value, in units of 16 bytes. This determines the window of time over which bandwidth is measured. For example, to measure bandwidth within a 1000 cycle window on a 64-bit interface is value 0x1F4.	`RW`	`0x8`

Bit

Name

Description

Access

Reset

9:0

SATURATION

In Bandwidth Limiter or Bandwidth Regulator mode, the maximum data count value, in units of 16 bytes. This determines the window of time over which bandwidth is measured. For example, to measure bandwidth within a 1000 cycle window on a 64-bit interface is value 0x1F4.

RW

0x8