no_of_blocks_per_lun

Module Instance	Base Address	Register Address
`sdm_i_nand_dma`	`0xFFA10700`	`0xFFA107A0`

Size: 32

Offset: 0xA0

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`			`issue_read_before_sync` `RW 0x0`	`Reserved`			`update_sync_before_prog_comp` `RW 0x0`	`Reserved`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved`												`value` `RW 0xF`

no_of_blocks_per_lun Fields

Bit	Name	Description	Access	Reset
28	`issue_read_before_sync`	Issue LOAD cmd to flash core even if SYNC condition is not satisfied. But the data is read from the device (for this load) only after the SYNC condition has been satisfied. If this value is 0, CMD DMA waits for SYNC before issuing a READ command. This bit should be set to 0 if the controller is being accessed in non-Command DMA mode.	`RW`	`0x0`
24	`update_sync_before_prog_comp`	Update SYNC Pointer after the data is written to flash and dont wait for program to complete. If this value is 0, CMD DMA waits for page program to get over before updating the sync pointer. This bit should be set to 0 if the controller is being accessed in non-Command DMA mode.	`RW`	`0x0`
3:0	`value`	Indicates the first block of next LUN. This information is used for extracting the target LUN during LUN interleaving. After Initialization, if the controller detects an ONFi device, this field is automatically updated by the controller. For other devices, software will need to write to this register for proper interleaving. The value in this register is interpreted as follows- [list][]0 - Next LUN starts from 1024. []1 - Next LUN starts from 2048. [*]2 - Next LUN starts from 4096 and so on... [/list]	`RW`	`0xF`

Bit

Name

Description

Access

Reset

issue_read_before_sync

Issue LOAD cmd to flash core even if SYNC condition is not satisfied. But the data is read 
                      from the device (for this load) only after the SYNC condition has been satisfied.
                      If this value is 0, CMD DMA waits for SYNC before issuing a READ command. 
                      This bit should be set to 0 if the controller is being accessed in non-Command DMA mode.

RW

0x0

update_sync_before_prog_comp

Update SYNC Pointer after the data is written to flash and dont wait for program 
                      to complete. If this value is 0, CMD DMA waits for page program to get over 
                      before updating the sync pointer. This bit should be set to 0 if the controller 
                      is being accessed in non-Command DMA mode.

RW

0x0

3:0

value

Indicates the first block of next LUN. This information is used for extracting the target LUN during LUN interleaving.
                        After Initialization, if the controller detects an ONFi device, 
                                       this field is automatically updated by the controller. 
                                       For other devices, software will need to write to this register 
                                       for proper interleaving.
                                       The value in this register is interpreted as follows-
                                       [list][*]0 - Next LUN starts from 1024.
                                             [*]1 - Next LUN starts from 2048.
                                             [*]2 - Next LUN starts from 4096 and so on...
                                       
                                       [/list]

RW

0xF