indaddrtrig

Module Instance	Base Address	Register Address
`sdm_qspi_qspiregs`	`0xFF8D2000`	`0xFF8D201C`

Size: 32

Offset: 0x1C

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`addr` `RW 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`addr` `RW 0x0`

indaddrtrig Fields

Bit	Name	Description	Access	Reset
31:0	`addr`	This is the base address that will be used by the AHB controller. When the incoming AHB read access address matches a range of addresses from this trigger address to the trigger address + 15, then the AHB request will be completed by fetching data from the Indirect Controllers SRAM.	`RW`	`0x0`

Bit

Name

Description

Access

Reset

31:0

addr

 This is the base address that will be used by the AHB controller. When the incoming AHB read access address matches a range of addresses from this trigger address to the trigger address + 15, then the AHB request will be completed by fetching data from the Indirect Controllers SRAM.

RW

0x0