sfe

         Shadow FIFO Enable
      
Module Instance Base Address Register Address
i_uart_0_uart_address_block 0xFFC02000 0xFFC02098
i_uart_1_uart_address_block 0xFFC02100 0xFFC02198

Size: 32

Offset: 0x98

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

rsvd_sfe_31to1

RO 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

rsvd_sfe_31to1

RO 0x0

sfe

RW 0x0

sfe Fields

Bit Name Description Access Reset
31:1 rsvd_sfe_31to1
Reserved bits [31:1] - Read Only
RO 0x0
0 sfe
Shadow FIFO Enable.
This is a shadow register for the FIFO enable bit (FCR[0]). This can be used to
remove the burden of having to store the previously written value to the FCR in
memory and having to mask this value so that only the FIFO enable bit gets updated.
This enables/disables the transmit (XMIT) and receive (RCVR) FIFO's. If this
bit is set to zero (disabled) after being enabled then both the XMIT and RCVR
controller portion of FIFO's will be reset.
Value Description
0 Disable Rx/Tx
1 Enable Rx/Tx
RW 0x0