SMMU_CB0_NMRR_MAIR1

         Normal memory remap register if AArch32 short descriptor scheme is selected. Provides additional mapping controls for memory regions that are mapped as Normal memory by their entry in SMMU_CBn_PRRR. Memory attribute indirection register when AArch32 Long descriptor scheme or AArch64 translation scheme is selected. Provide a revised version of the TEX-Remap system to redirect the selection of memory attributes from the translation table entries.
      
Note: For register and programming information, please refer to the Arm® CoreLink™ MMU System Memory Management Unit Technical Reference Manual.
Module Instance Base Address Register Address
i_aps_smmu_secure_registers 0xFA000000 0xFA02003C

Size: 32

Offset: 0x2003C

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

OR7

RW 0x0

OR6

RW 0x0

OR5

RW 0x0

OR4

RW 0x0

OR3

RW 0x0

OR2

RW 0x0

OR1

RW 0x0

OR0

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

IR7

RW 0x0

IR6

RW 0x0

IR5

RW 0x0

IR4

RW 0x0

IR3

RW 0x0

IR2

RW 0x0

IR1

RW 0x0

IR0

RW 0x0