IC_TXFLR

         Name: I2C Transmit FIFO Level Register
Size: TX_ABW + 1
Address Offset: 0x74
Read/Write Access: Read
This register contains the number of valid data
entries in the transmit FIFO buffer. It is cleared
whenever:
- The I2C is disabled
- There is a transmit abort that is, TX_ABRT bit is
  set in the IC_RAW_INTR_STAT register
- The slave bulk transmit mode is aborted
The register increments whenever data is placed into
the transmit FIFO and decrements when data is
taken from the transmit FIFO.
      
Module Instance Base Address Register Address
sdm_i2c_0_DW_apb_i2c_addr_block0 0xFF8D0100 0xFF8D0174
sdm_i2c_1_DW_apb_i2c_addr_block1 0xFF8D0200 0xFF8D0274

Size: 32

Offset: 0x74

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RSVD_TXFLR

RO 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RSVD_TXFLR

RO 0x0

TXFLR

RO 0x0

IC_TXFLR Fields

Bit Name Description Access Reset
31:7 RSVD_TXFLR
Reserved bits - Read Only
RO 0x0
6:0 TXFLR
Transmit FIFO Level.
Contains the number of valid data entries in the
transmit FIFO.
Reset value: 0x0
RO 0x0