LCR
Line Control Register
| Module Instance | Base Address | Register Address |
|---|---|---|
| i_uart_uart_address_block | 0xFF8D0000 | 0xFF8D000C |
Size: 32
Offset: 0xC
Access: RW
| Bit Fields | |||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|
RSVD_LCR_31to8 RO 0x0 |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
RSVD_LCR_31to8 RO 0x0 |
DLAB RW 0x0 |
Break RW 0x0 |
SP RW 0x0 |
EPS RW 0x0 |
PEN RW 0x0 |
STOP RW 0x0 |
DLS RW 0x0 |
||||||||
LCR Fields
| Bit | Name | Description | Access | Reset | ||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31:8 | RSVD_LCR_31to8 |
Reserved bits [31:8] - Read Only |
RO | 0x0 | ||||||||||
| 7 | DLAB |
Divisor Latch Access Bit. If UART_16550_COMPATIBLE == NO then, writeable only when UART is not busy (USR[0] is zero), otherwise always writable, always readable. This bit is used to enable reading and writing of the Divisor Latch register (DLL and DLH) to set the baud rate of the UART. This bit must be cleared after initial baud rate setup in order to access other registers.
|
RW | 0x0 | ||||||||||
| 6 | Break |
Break Control Bit. This is used to cause a break condition to be transmitted to the receiving device. If set to one the serial output is forced to the spacing (logic 0) state. When not in Loopback Mode, as determined by MCR[4], the sout line is forced low until the Break bit is cleared. If SIR_MODE == Enabled and active (MCR[6] set to one) the sir_out_n line is continuously pulsed. When in Loopback Mode, the break condition is internally looped back to the receiver and the sir_out_n line is forced low.
|
RW | 0x0 | ||||||||||
| 5 | SP |
From DW_apb_uart_regfile.sv:
// aaraujo @ 17/05/2011 : CRM_9000431453
// Stick parity lcr_ir[5] is now programmable
lcr_ir[5:0] <= ipwdata[5:0];
|
RW | 0x0 | ||||||||||
| 4 | EPS |
Even Parity Select. If UART_16550_COMPATIBLE == NO then, writeable only when UART is not busy (USR[0] is zero), otherwise always writable, always readable. This is used to select between even and odd parity, when parity is enabled (PEN set to one). If set to one, an even number of logic '1's is transmitted or checked. If set to zero, an odd number of logic '1's is transmitted or checked.
|
RW | 0x0 | ||||||||||
| 3 | PEN |
Parity Enable. If UART_16550_COMPATIBLE == NO then, writeable only when UART is not busy (USR[0] is zero), otherwise always writable, always readable. This bit is used to enable and disable parity generation and detection in transmitted and received serial character respectively. 0 = parity disabled 1 = parity enabled
|
RW | 0x0 | ||||||||||
| 2 | STOP |
Number of stop bits. If UART_16550_COMPATIBLE == NO then, writeable only when UART is not busy (USR[0] is zero), otherwise always writable, always readable. This is used to select the number of stop bits per character that the peripheral will transmit and receive. If set to zero, one stop bit is transmitted in the serial data. If set to one and the data bits are set to 5 (LCR[1:0] set to zero) one and a half stop bits is transmitted. Otherwise, two stop bits are transmitted. Note that regardless of the number of stop bits selected the receiver will only check the first stop bit. 0 = 1 stop bit 1 = 1.5 stop bits when DLS (LCR[1:0]) is zero, else 2 stop bit
|
RW | 0x0 | ||||||||||
| 1:0 | DLS |
Data Length Select. If UART_16550_COMPATIBLE == NO then, writeable only when UART is not busy (USR[0] is zero), otherwise always writable, always readable. This is used to select the number of data bits per character that the peripheral will transmit and receive. The number of bit that may be selected are as follows: 00 = 5 bits 01 = 6 bits 10 = 7 bits 11 = 8 bits
|
RW | 0x0 |