ddr_T_main_Probe_Filters_3_Opcode

         
	Packet Probe register Opcode is a 4-bit register that selects candidate packets based on packet opcodes (0 disables the filter):

Module Instance	Base Address	Register Address
`soc_ddr_scheduler_inst_0_ddr_T_main_Probe`	`0xF8000000`	`0xF8000114`

Size: 32

Offset: 0x114

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved`												`URGEN` `RW 0x0`	`LOCKEN` `RW 0x0`	`WREN` `RW 0x0`	`RDEN` `RW 0x0`

ddr_T_main_Probe_Filters_3_Opcode Fields

Bit	Name	Description	Access	Reset
3	`URGEN`	Selects URG packets (urgency).	`RW`	`0x0`
2	`LOCKEN`	Selects RDX-WR, RDL, WRC and Linked sequence.	`RW`	`0x0`
1	`WREN`	Selects WR packets.	`RW`	`0x0`
0	`RDEN`	Selects RD packets.	`RW`	`0x0`