ddr_T_main_Probe_StatPeriod

         DDR Main Probe Statistics Period Register
      
Module Instance Base Address Register Address
soc_ddr_scheduler_inst_0_ddr_T_main_Probe 0xF8000000 0xF8000024

Size: 32

Offset: 0x24

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

STATPERIOD

RW 0x0

ddr_T_main_Probe_StatPeriod Fields

Bit Name Description Access Reset
4:0 STATPERIOD
Register StatPeriod is a 5-bit register that sets a period, within a range of 2 cycles to 2 gigacycles, during which statistics are collected before being dumped automatically. Setting the register implicitly enables automatic mode operation for statistics collection. The period is calculated with the formula: N_Cycle = 2**StatPeriodWhen register StatPeriod is set to its default value 0, automatic dump mode is disabled, and register StatGo is activated for manual mode operation. Note: When parameter statisticsCollection is set to False, StatPeriod is reserved.
RW 0x0