jtag

         Jtag control registers for the  PLLs

Module Instance	Base Address	Register Address
`i_clk_mgr_jtaggrp`	`0xFFD10128`	`0xFFD10128`

Size: 32

Offset: 0x0

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved`							`rst` `RW 0x1`	`addr` `RW 0x80`

jtag Fields

Bit	Name	Description	Access	Reset
8	`rst`	Jtag rst signal. Its an active low signal. 1- reset de-asserted 0- reset asserted	`RW`	`0x1`
7:0	`addr`	JTAG address for both the PLLs	`RW`	`0x80`