reg_sideband5

         Sideband 5 Register

Module Instance	Base Address	Register Address
`iohmc_ctrl_inst_0_iohmc_ctrl_mmr_top_inst`	`0xF8010000`	`0xF80100C0`

Size: 32

Offset: 0xC0

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved`															`mmr_dpd_mps_req` `RW 0x0`

reg_sideband5 Fields

Bit	Name	Description	Access	Reset
0	`mmr_dpd_mps_req`	iohmc_ctrl_mmr_top_inst.mmr_dpd_mps_req Name:User Deep Power Down/Max Power Saving Request Description:Asserting this bit will enter deep power down/maximum power saving mode. User must poll acknowledge. Once acknowledge goes high, indicating DPD/MPS entry, user may de-assert (exit DPD/MPS) or keep this bit asserted (to maintain DPD/MPS).	`RW`	`0x0`

Bit

Name

Description

Access

Reset

mmr_dpd_mps_req

iohmc_ctrl_mmr_top_inst.mmr_dpd_mps_req
Name:User Deep Power Down/Max Power Saving Request
Description:Asserting this bit will enter deep power down/maximum power saving mode. User must poll acknowledge. Once acknowledge goes high, indicating DPD/MPS entry, user may de-assert (exit DPD/MPS) or keep this bit asserted (to maintain DPD/MPS).

RW

0x0