reg_sideband0 

         Sideband 0 Register
Module Instance Base Address Register Address
iohmc_ctrl_inst_0_iohmc_ctrl_mmr_top_inst 0xF8010000 0xF80100AC

Size: 32

Offset: 0xAC

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

mr_cmd_trigger

RW 0x0

reg_sideband0 Fields

Bit Name Description Access Reset
0 mr_cmd_trigger 
iohmc_ctrl_mmr_top_inst.mr_cmd_trigger
Name:Mode Register Command Execution Trigger
Description:When asserted indicates user request to execute mode register command. Controller clear bit to 0 once operation completed.
RW 0x0