gmacgrp_l3_l4_control0 

          Register 256 (Layer 3 and Layer 4 Control Register 0) 

This register controls the operations of the filter 0 of Layer 3 and Layer 4. This register is reserved if the Layer 3 and Layer 4 Filtering feature is not selected during core configuration.
Module Instance Base Address Register Address
i_emac_emac0 0xFF800000 0xFF800400
i_emac_emac1 0xFF802000 0xFF802400
i_emac_emac2 0xFF804000 0xFF804400

Size: 32

Offset: 0x400

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

reserved_31_22

RO 0x0

l4dpim0

RW 0x0

l4dpm0

RW 0x0

l4spim0

RW 0x0

l4spm0

RW 0x0

reserved_17

RO 0x0

l4pen0

RW 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

l3hdbm0

RW 0x0

l3hsbm0

RW 0x0

l3daim0

RW 0x0

l3dam0

RW 0x0

l3saim0

RW 0x0

l3sam0

RW 0x0

reserved_1

RO 0x0

l3pen0

RW 0x0

gmacgrp_l3_l4_control0 Fields

Bit Name Description Access Reset
31:22 reserved_31_22 
Reserved
 RO 0x0
21 l4dpim0 
Layer 4 Destination Port Inverse Match Enable

When set, this bit indicates that the Layer 4 Destination Port number field is enabled for inverse matching. When reset, this bit indicates that the Layer 4 Destination Port number field is enabled for perfect matching.

This bit is valid and applicable only when Bit 20 (L4DPM0) is set high.
 RW 0x0
20 l4dpm0 
Layer 4 Destination Port Match Enable

When set, this bit indicates that the Layer 4 Destination Port number field is enabled for matching. When reset, the MAC ignores the Layer 4 Destination Port number field for matching.
 RW 0x0
19 l4spim0 
Layer 4 Source Port Inverse Match Enable

When set, this bit indicates that the Layer 4 Source Port number field is enabled for inverse matching. When reset, this bit indicates that the Layer 4 Source Port number field is enabled for perfect matching.

This bit is valid and applicable only when Bit 18 (L4SPM0) is set high.
 RW 0x0
18 l4spm0 
Layer 4 Source Port Match Enable

When set, this bit indicates that the Layer 4 Source Port number field is enabled for matching. When reset, the MAC ignores the Layer 4 Source Port number field for matching.
 RW 0x0
17 reserved_17 
Reserved
 RO 0x0
16 l4pen0 
Layer 4 Protocol Enable

When set, this bit indicates that the Source and Destination Port number fields for UDP frames are used for matching. When reset, this bit indicates that the Source and Destination Port number fields for TCP frames are used for matching.

The Layer 4 matching is done only when either L4SPM0 or L4DPM0 bit is set high.
 RW 0x0
15:11 l3hdbm0 
Layer 3 IP DA Higher Bits Match

IPv4 Frames: 

This field contains the number of higher bits of IP Destination Address that are matched in the IPv4 frames. The following list describes the values of this field:
 * 0: No bits are masked.
 * 1: LSb[0] is masked.
 * 2: Two LSbs [1:0] are masked.
 * ...
 * 31: All bits except MSb are masked.
IPv6 Frames: 

Bits [12:11] of this field correspond to Bits [6:5] of L3HSBM0, which indicate the number of lower bits of IP Source or Destination Address that are masked in the IPv6 frames. The following list describes the concatenated values of the L3HDBM0[1:0] and L3HSBM0 bits:
 * 0: No bits are masked.
 * 1: LSb[0] is masked.
 * 2: Two LSbs [1:0] are masked.
 * ...
 * 127: All bits except MSb are masked.
This field is valid and applicable only if L3DAM0 or L3SAM0 is set high.
 RW 0x0
10:6 l3hsbm0 
Layer 3 IP SA Higher Bits Match

IPv4 Frames: 

This field contains the number of lower bits of IP Source Address that are masked for matching in the IPv4 frames. The following list describes the values of this field:
 * 0: No bits are masked.
 * 1: LSb[0] is masked.
 * 2: Two LSbs [1:0] are masked.
 * ...
 * 31: All bits except MSb are masked.
IPv6 Frames: 

This field contains Bits [4:0] of the field that indicates the number of higher bits of IP Source or Destination Address matched in the IPv6 frames.
This field is valid and applicable only if L3DAM0 or L3SAM0 is set high.
 RW 0x0
5 l3daim0 
Layer 3 IP DA Inverse Match Enable

When set, this bit indicates that the Layer 3 IP Destination Address field is enabled for inverse matching. When reset, this bit indicates that the Layer 3 IP Destination Address field is enabled for perfect matching.

This bit is valid and applicable only when Bit 4 (L3DAM0) is set high.
 RW 0x0
4 l3dam0 
Layer 3 IP DA Match Enable

When set, this bit indicates that Layer 3 IP Destination Address field is enabled for matching. When reset, the MAC ignores the Layer 3 IP Destination Address field for matching.

Note: When Bit 0 (L3PEN0) is set, you should set either this bit or Bit 2 (L3SAM0) because either IPv6 DA or SA can be checked for filtering.
 RW 0x0
3 l3saim0 
Layer 3 IP SA Inverse Match Enable

When set, this bit indicates that the Layer 3 IP Source Address field is enabled for inverse matching. When reset, this bit indicates that the Layer 3 IP Source Address field is enabled for perfect matching.

This bit is valid and applicable only when Bit 2 (L3SAM0) is set high.
 RW 0x0
2 l3sam0 
Layer 3 IP SA Match Enable

When set, this bit indicates that the Layer 3 IP Source Address field is enabled for matching. When reset, the MAC ignores the Layer 3 IP Source Address field for matching.

Note: When Bit 0 (L3PEN0) is set, you should set either this bit or Bit 4 (L3DAM0) because either IPv6 SA or DA can be checked for filtering.
 RW 0x0
1 reserved_1 
Reserved
 RO 0x0
0 l3pen0 
Layer 3 Protocol Enable

When set, this bit indicates that the Layer 3 IP Source or Destination Address matching is enabled for the IPv6 frames. When reset, this bit indicates that the Layer 3 IP Source or Destination Address matching is enabled for the IPv4 frames.

The Layer 3 matching is done only when either L3SAM0 or L3DAM0 bit is set high.
 RW 0x0