GICH_MISR

         Maintenance Interrupt Status Register

Note: For register and programming information, please refer to the Arm^® CoreLink™ GIC-400 Generic Interrupt Controller Technical Reference Manual.

Module Instance	Base Address	Register Address
`i_gic_wrapper_VCPUifHypAlias7`	`0xFFFC5E00`	`0xFFFC5E10`

Size: 32

Offset: 0x10

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.