tfl
| Module Instance | Base Address | Register Address |
|---|---|---|
| i_uart_0_uart_address_block | 0xFFC02000 | 0xFFC02080 |
| i_uart_1_uart_address_block | 0xFFC02100 | 0xFFC02180 |
Size: 32
Offset: 0x80
Access: RO
Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
| Bit Fields | |||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|
rsvd_tfl_31toaddr_width RO 0x0 |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
rsvd_tfl_31toaddr_width RO 0x0 |
tfl RO 0x0 |
||||||||||||||
tfl Fields
| Bit | Name | Description | Access | Reset |
|---|---|---|---|---|
| 31:8 | rsvd_tfl_31toaddr_width |
Reserved bits: 31 downto addr bus width + 1 - Read Only |
RO | 0x0 |
| 7:0 | tfl |
Transmit FIFO Level. This is indicates the number of data entries in the transmit FIFO. |
RO | 0x0 |