gmacgrp_rxalignmenterror
Register 102 (Receive Frame Count for Alignment Error Frames)
This register maintains the number of frames received with alignment (dribble) error. This field is valid only in the 10 or 100 Mbps mode.
| Module Instance | Base Address | Register Address |
|---|---|---|
| i_emac_emac0 | 0xFF800000 | 0xFF800198 |
| i_emac_emac1 | 0xFF802000 | 0xFF802198 |
| i_emac_emac2 | 0xFF804000 | 0xFF804198 |
Size: 32
Offset: 0x198
Access: RO
Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
| Bit Fields | |||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
|
cnt RO 0x0 |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|
cnt RO 0x0 |
|||||||||||||||
gmacgrp_rxalignmenterror Fields
| Bit | Name | Description | Access | Reset |
|---|---|---|---|---|
| 31:0 | cnt |
This field indicates the number of frames received with alignment (dribble) error. This field is valid only in the 10 or 100 Mbps mode. |
RO | 0x0 |