reg_ctrlcfg5
Module Instance Base Address Register Address
iohmc_ctrl_inst_0_iohmc_ctrl_mmr_top_inst 0xF8010000 0xF801003C

Size: 32

Offset: 0x3C

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

cfg_dbc3_rc_en

RW 0x0

cfg_dbc2_rc_en

RW 0x0

cfg_dbc1_rc_en

RW 0x0

cfg_dbc0_rc_en

RW 0x0

cfg_ctrl_rc_en

RW 0x0

cfg_row_cmd_slot

RW 0x0

cfg_col_cmd_slot

RW 0x0

reg_ctrlcfg5 Fields

Bit Name Description Access Reset
12 cfg_dbc3_rc_en 
iohmc_ctrl_mmr_top_inst.cfg_dbc3_rc_en
Name:DBC3 Rate Conversion Enable
Description:Set to 1 to enable the rate conversion. It converts QR input from core to HR inside HMC
RW 0x0
11 cfg_dbc2_rc_en 
iohmc_ctrl_mmr_top_inst.cfg_dbc2_rc_en
Name:DBC2 Rate Conversion Enable
Description:Set to 1 to enable the rate conversion. It converts QR input from core to HR inside HMC
RW 0x0
10 cfg_dbc1_rc_en 
iohmc_ctrl_mmr_top_inst.cfg_dbc1_rc_en
Name:DBC1 Rate Conversion Enable
Description:Set to 1 to enable the rate conversion. It converts QR input from core to HR inside HMC
RW 0x0
9 cfg_dbc0_rc_en 
iohmc_ctrl_mmr_top_inst.cfg_dbc0_rc_en
Name:DBC0 Rate Conversion Enable
Description:Set to 1 to enable the rate conversion. It converts QR input from core to HR inside HMC
RW 0x0
8 cfg_ctrl_rc_en 
iohmc_ctrl_mmr_top_inst.cfg_ctrl_rc_en
Name:Control Path Rate Conversion Enable
Description:Set to 1 to enable the rate conversion. It converts QR input from core to HR inside HMC
RW 0x0
7:4 cfg_row_cmd_slot 
iohmc_ctrl_mmr_top_inst.cfg_row_cmd_slot[3:0]
Name:Row Cmd Slot
Description:Specify the row cmd slot. One hot encoding.
RW 0x0
3:0 cfg_col_cmd_slot 
iohmc_ctrl_mmr_top_inst.cfg_col_cmd_slot[3:0]
Name:Column Cmd Slot
Description:Specify the col cmd slot. One hot encoding.
RW 0x0