stat

Consist of control bit and status information.

Module Instance	Base Address	Register Address
`scanmgr`	`0xFFF02000`	`0xFFF02000`

Offset: 0x0

Access: RW

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`active` `RO 0x0`	`wfifocnt` `RO 0x0`			`Reserved`	`rfifocnt` `RO 0x0`			`Reserved`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved`												`ignore` `RO 0x0`	`Reserved`	`trst` `RW 0x0`	`Reserved`

stat Fields

Bit

Name

Description

Access

Reset

active

Indicates if the Scan-Chain Engine is processing commands from the Command FIFO or not. The Scan-Chain Engine is only guaranteed to be inactive if both the ACTIVE and WFIFOCNT fields are zero. The name of this field in documentation is SERACTV.

Value	Description
0x0	The Scan-Chain Engine may or may not be processing commands from the Command FIFO. The Scan-Chain Engine is only guaranteed to be inactive if both this ACTIVE field and the WFIFOCNT fields are both zero.
0x1	The Scan-Chain Engine is processing commands from the Command FIFO.

RO

0x0

30:28

wfifocnt

Command FIFO outstanding byte count. Returns the number of command bytes held in the Command FIFO that have yet to be processed by the Scan-Chain Engine.

RO

0x0

26:24

rfifocnt

Response FIFO outstanding byte count. Returns the number of bytes of response data available in the Response FIFO.

RO

0x0

ignore

Ignore this field. Its value is undefined (may be 0 or 1). The name of this field in documentation is PORTCONNECTED.

RO

0x0

trst

Specifies the value of the nTRST signal driven to the FPGA JTAG only. The FPGA JTAG scan-chain must be enabled via the EN register to drive the value specified in this field. The nTRST signal is driven with the inverted value of this field.The nTRST signal is active low so, when this bit is set to 1, FPGA JTAG is reset. The name of this field in documentation is TRST_OUT.

Value	Description
0x0	Don't reset FPGA JTAG.
0x1	Reset FPGA JTAG. Must have the FPGA JTAG scan-chain enabled in the EN register to take effect.

RW

0x0