CTR

The Test Mode is entered by setting bit CCTRL.Test to one. In Test Mode the bits EXL, Tx1, Tx0, LBack and Silent in the Test Register are writable. Bit Rx monitors the state of pin CAN_RXD and therefore is only readable. All Test Register functions are disabled when bit Test is reset to zero. Loop Back Mode and CAN_TXD Control Mode are hardware test modes, not to be used by application programs. Note: This register is only writable if bit CCTRL.Test is set.

Module Instance	Base Address	Register Address
`can0`	`0xFFC00000`	`0xFFC00014`
`can1`	`0xFFC01000`	`0xFFC01014`

Offset: 0x14

Access: RW

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved`								`Rx` `RO 0x0`	`Tx` `RW 0x0`		`LBack` `RW 0x0`	`Silent` `RW 0x0`	`Reserved`

CTR Fields

Bit

Name

Description

Access

Reset

Rx

Monitors the actual value of the CAN_RXD pin.

Value	Description
0x0	The CAN bus is dominant (CAN_RXD = 0).
0x1	The CAN bus is recessive (CAN_RXD = 1).

RO

0x0

6:5

Tx

Controls CAN_TXD pin. Setting to non-zero disturbs message transfer.

Value	Description
0x0	Reset value, CAN_TXD is controlled by the CAN_Core.
0x1	Sample Point can be monitored at CAN_TXD pin.
0x2	CAN_TXD pin drives a dominant (0) value.
0x3	CAN_TXD pin drives a recessive (1) value.

RW

0x0

LBack

Loop Back Mode

Value	Description
0x0	Loop Back Mode is disabled.
0x1	Loop Back Mode is enabled.

RW

0x0

Silent

Silent Mode

Value	Description
0x0	Normal operation.
0x1	The CAN is in Silent Mode.

RW

0x0