CIR
If several interrupts are pending, the CAN Interrupt Register will point to the pending interrupt with the highest priority, disregarding their chronological order. An interrupt remains pending until the CPU has cleared it. If IntID is different from 0x00 and CCTRL.MIL is set, the interrupt port CAN_INT_MO is active. The interrupt port remains active until IntID is back to value 0x00 (the cause of the interrupt is reset) or until CCTRL.MIL is reset. If CCTRL.ILE is set and CCTRL.MIL is reseted the Message Object interrupts will be routed to interrupt port CAN_INT_STATUS. The interrupt port remains active until IntID is back to value 0x00 (the cause of the interrupt is reset) or until CCTRL.MIL is set or CCTRL.ILE is reset.
The Message Object's interrupt priority decreases with increasing message number.
A message interrupt is cleared by clearing the Message Object's IntPnd bit.
| Module Instance | Base Address | Register Address |
|---|---|---|
| can0 | 0xFFC00000 | 0xFFC00010 |
| can1 | 0xFFC01000 | 0xFFC01010 |
Offset: 0x10
Access: RO
Important: To prevent indeterminate
system behavior, reserved areas of memory must not be accessed by software or
hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
| Bit Fields | |||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
Reserved |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
StatusInt RO 0x0 |
Reserved |
IntId RO 0x0 |
|||||||||||||
CIR Fields
| Bit | Name | Description | Access | Reset |
|---|---|---|---|---|
| 15 | StatusInt | The Status Interrupt is cleared by reading the Status Register. |
RO | 0x0 |
| 7:0 | IntId | 0x00 No Message Object interrupt is pending. 0x01-0x80 Number of Message Object which caused the interrupt. 0x81-0xFF unused. |
RO | 0x0 |