CERC
Error Counter Register
| Module Instance | Base Address | Register Address |
|---|---|---|
| can0 | 0xFFC00000 | 0xFFC00008 |
| can1 | 0xFFC01000 | 0xFFC01008 |
Offset: 0x8
Access: RO
Important: To prevent indeterminate
system behavior, reserved areas of memory must not be accessed by software or
hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
| Bit Fields | |||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
Reserved |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RP RO 0x0 |
REC RO 0x0 |
TEC RO 0x0 |
|||||||||||||
CERC Fields
| Bit | Name | Description | Access | Reset | ||||||
|---|---|---|---|---|---|---|---|---|---|---|
| 15 | RP |
|
RO | 0x0 | ||||||
| 14:8 | REC | Actual state of the Receive Error Counter. Values between 0 and 127. |
RO | 0x0 | ||||||
| 7:0 | TEC | Actual state of the Transmit Error Counter. Values between 0 and 255. |
RO | 0x0 |