wdt_comp_param_1

This is a constant read-only register that contains encoded information about the component's parameter settings.

Module Instance	Base Address	Register Address
`l4wd0`	`0xFFD02000`	`0xFFD020F4`
`l4wd1`	`0xFFD03000`	`0xFFD030F4`

Offset: 0xF4

Access: RO

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`			`cp_wdt_cnt_width` `RO 0x10`					`cp_wdt_dflt_top_init` `RO 0xF`				`cp_wdt_dflt_top` `RO 0xF`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved`			`cp_wdt_dflt_rpl` `RO 0x0`			`cp_wdt_apb_data_width` `RO 0x2`		`cp_wdt_pause` `RO 0x0`	`cp_wdt_use_fix_top` `RO 0x1`	`cp_wdt_hc_top` `RO 0x0`	`cp_wdt_hc_rpl` `RO 0x1`	`cp_wdt_hc_rmod` `RO 0x0`	`cp_wdt_dual_top` `RO 0x1`	`cp_wdt_dflt_rmod` `RO 0x0`	`cp_wdt_always_en` `RO 0x0`

wdt_comp_param_1 Fields

Bit

Name

Description

Access

Reset

28:24

cp_wdt_cnt_width

Width of counter in bits less 16.

Value	Description
0x10	Counter width is 32 bits

RO

0x10

23:20

cp_wdt_dflt_top_init

Specifies the initial timeout period that is available directly after reset.

Value	Description
0xf	Initial timeout period is 15 (2**31 cycles).

RO

0xF

19:16

cp_wdt_dflt_top

Specifies the timeout period that is available directly after reset.

Value	Description
0xf	Timeout period is 15 (2**31 cycles).

RO

0xF

12:10

cp_wdt_dflt_rpl

Specifies the reset pulse length in cycles.

Value	Description
0x0	Reset pulse length of 2 cycles.

RO

0x0

9:8

cp_wdt_apb_data_width

APB Bus Width

Value	Description
0x2	APB Data Width is 32 Bits

RO

0x2

cp_wdt_pause

Should specify if the pause input is included or not. However, this field is always hardwired to 0 so you can't figure this out by reading this field. The pause input is included and can be used to pause the watchdog when the MPU is in debug mode.

RO

0x0

cp_wdt_use_fix_top

Specifies if the watchdog uses the pre-defined timeout values or if these were overriden with customer values when the watchdog was configured.

Value	Description
0x1	Use pre-defined (fixed) timeout values (range from 216 to 231)

RO

0x1

cp_wdt_hc_top

Specifies if the timeout period is programmable or hardcoded.

Value	Description
0x0	Timeout period is programmable.

RO

0x0

cp_wdt_hc_rpl

Specifies if the reset pulse length is programmable or hardcoded.

Value	Description
0x1	Reset pulse length is hardcoded.

RO

0x1

cp_wdt_hc_rmod

Specifies if response mode (when counter reaches 0) is programmable or hardcoded.

Value	Description
0x0	Output response mode is programmable.

RO

0x0

cp_wdt_dual_top

Specifies whether a second timeout period that is used for initialization prior to the first kick is present or not.

Value	Description
0x1	Second timeout period is present

RO

0x1

cp_wdt_dflt_rmod

Specifies default output response mode after reset.

Value	Description
0x0	Generate a warm reset request (don't generate an interrupt first)

RO

0x0

cp_wdt_always_en

Specifies whether watchdog starts after reset or not.

Value	Description
0x0	Watchdog disabled on reset

RO

0x0