timerseoi
Clears Timer1 interrupt when read. Because there is only Timer1 in this module instance, reading this register has the same effect as reading timer1eoi.
| Module Instance | Base Address | Register Address |
|---|---|---|
| sptimer0 | 0xFFC08000 | 0xFFC080A4 |
| sptimer1 | 0xFFC09000 | 0xFFC090A4 |
| osc1timer0 | 0xFFD00000 | 0xFFD000A4 |
| osc1timer1 | 0xFFD01000 | 0xFFD010A4 |
Offset: 0xA4
Access: RO
Important: To prevent indeterminate
system behavior, reserved areas of memory must not be accessed by software or
hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
| Bit Fields | |||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
Reserved |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved |
timerseoi RO 0x0 |
||||||||||||||
timerseoi Fields
| Bit | Name | Description | Access | Reset |
|---|---|---|---|---|
| 0 | timerseoi | Reading from this register clears the interrupt all timers and returns 0. Because there is only Timer1 in this module instance, reading this register has the same effect as reading timer1eoi. |
RO | 0x0 |