timersintstat
Provides the interrupt status for all timers after masking. Because there is only Timer1 in this module instance, this status is the same as timer1intstat.
| Module Instance | Base Address | Register Address |
|---|---|---|
| sptimer0 | 0xFFC08000 | 0xFFC080A0 |
| sptimer1 | 0xFFC09000 | 0xFFC090A0 |
| osc1timer0 | 0xFFD00000 | 0xFFD000A0 |
| osc1timer1 | 0xFFD01000 | 0xFFD010A0 |
Offset: 0xA0
Access: RO
Important: To prevent indeterminate
system behavior, reserved areas of memory must not be accessed by software or
hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
| Bit Fields | |||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
Reserved |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved |
timersintstat RO 0x0 |
||||||||||||||
timersintstat Fields
| Bit | Name | Description | Access | Reset | ||||||
|---|---|---|---|---|---|---|---|---|---|---|
| 0 | timersintstat | Provides the interrupt status for Timer1. Because there is only Timer1 in this module instance, this status is the same as timer1intstat. The status reported is after the interrupt mask has been applied. Reading from this register does not clear any active interrupts.
|
RO | 0x0 |