timer1controlreg
This register controls enabling, operating mode (free-running or user-defined-count), and interrupt mask of Timer1. You can program this register to enable or disable Timer1 and to control its mode of operation.
| Module Instance | Base Address | Register Address |
|---|---|---|
| sptimer0 | 0xFFC08000 | 0xFFC08008 |
| sptimer1 | 0xFFC09000 | 0xFFC09008 |
| osc1timer0 | 0xFFD00000 | 0xFFD00008 |
| osc1timer1 | 0xFFD01000 | 0xFFD01008 |
Offset: 0x8
Access: RW
Important: To prevent indeterminate
system behavior, reserved areas of memory must not be accessed by software or
hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
| Bit Fields | |||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
Reserved |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved |
timer1_interrupt_mask RW 0x0 |
timer1_mode RW 0x0 |
timer1_enable RW 0x0 |
||||||||||||
timer1controlreg Fields
| Bit | Name | Description | Access | Reset | ||||||
|---|---|---|---|---|---|---|---|---|---|---|
| 2 | timer1_interrupt_mask | Timer1 interrupt mask
|
RW | 0x0 | ||||||
| 1 | timer1_mode | Sets operating mode. NOTE: You must set the timer1loadcount register to all ones before enabling the timer in free-running mode.
|
RW | 0x0 | ||||||
| 0 | timer1_enable | Timer1 enable/disable bit.
|
RW | 0x0 |