gpio_porta_eoi
Port A Data Register interrupt handling.
| Module Instance | Base Address | Register Address |
|---|---|---|
| gpio0 | 0xFF708000 | 0xFF70804C |
| gpio1 | 0xFF709000 | 0xFF70904C |
| gpio2 | 0xFF70A000 | 0xFF70A04C |
Offset: 0x4C
Access: WO
Important: To prevent indeterminate
system behavior, reserved areas of memory must not be accessed by software or
hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
| Bit Fields | |||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
Reserved |
gpio_porta_eoi WO 0x0 |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
gpio_porta_eoi WO 0x0 |
|||||||||||||||
gpio_porta_eoi Fields
| Bit | Name | Description | Access | Reset | ||||||
|---|---|---|---|---|---|---|---|---|---|---|
| 28:0 | gpio_porta_eoi | Controls the clearing of edge type interrupts from the Port A Data Register. Note that only bits[26:0] are implemented for gpio2.
|
WO | 0x0 |