gpio_int_polarity
Controls the Polarity of Interrupts that can occur on inputs of Port A Data Register
| Module Instance | Base Address | Register Address |
|---|---|---|
| gpio0 | 0xFF708000 | 0xFF70803C |
| gpio1 | 0xFF709000 | 0xFF70903C |
| gpio2 | 0xFF70A000 | 0xFF70A03C |
Offset: 0x3C
Access: RW
Important: To prevent indeterminate
system behavior, reserved areas of memory must not be accessed by software or
hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
| Bit Fields | |||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
Reserved |
gpio_int_polarity RW 0x0 |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
gpio_int_polarity RW 0x0 |
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gpio_int_polarity Fields
| Bit | Name | Description | Access | Reset | ||||||
|---|---|---|---|---|---|---|---|---|---|---|
| 28:0 | gpio_int_polarity | Controls the polarity of edge or level sensitivity that can occur on input of Port A Data Register. Note that only bits[26:0] are implemented for gpio2.
|
RW | 0x0 |